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Universal Verification Methodology Based Verification Environment

Jain:Universal Verification Methodology
Autor: Abhishek Jain
Verfügbarkeit: nur noch 3 lieferbar
Artikelnummer: 1377348
ISBN / EAN: 9783659476044

Verfügbarkeit: sofort lieferbar

36,90
Inkl. MwSt. , zzgl. Versandkosten

Produktbeschreibung

Ever increasing silicon design complexity and transistor density, product differentiation and time to market are major factors creating huge pressure on complete design flow. This book covers Verification phase by describing the concepts of Universal Verification Methodology (UVM) and by presenting a pragmatic approach of developing efficient and unified advanced verification environment at all levels using Universal Verification Methodology along with Assertion based verification, hardware acceleration and Transaction Level Modeling. This book is written primarily for verification engineers performing verification of complex IP blocks or entire system-on-chip (SoC) designs. However, much of material will also be of interest to SoC project managers as well as designers to learn more about verification. Furthermore, this book includes detailed information about verification environment for one case which can be easily used as reference for other cases.

Zusatzinformation

Autor Verlag LAP Lambert Academic Publishing
ISBN / EAN 9783659476044 Bindung Taschenbuch

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